74LV00 datasheet pdf
| Subject | 74LV00 datasheet pdf |
| Company | PHILIPS |
| Site | http://www.nxp.com |
| Datetime | 09-19 |
| Download | 74LV00 |
74LV00 Datasheet PDF Download and Image Preview.
Quad 2-input NAND gate.
It provides basic pin configuration information, and includes information about internal structure block diagrams and pin descriptions.
A summary of the 74LV00 instruction set is provided. The image below is a summary. For detailed information on pinout and circuit system operation, please refer to the attached file.
Manufacturer : PHILIPS
74LV00 Features
1. Low forward voltage drop
2. Low leakage current
3. High forward surge capability
4. Solder dip 275 °C max. 10 s, per JESD 22-B106
5. Compliant to RoHS Directive 2002/95/EC and in
6. accordance to WEEE 2002/96/EC
DESCRIPTION
The 74LV00 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT00.
The 74LV00 provides the 2-input NAND function.
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 fi (CL VCC2 fo) where:
fi
= input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 fi (CL VCC2 fo) where:
fi
= input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC
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